The present invention relates to an interconnecting method for a semiconductor device, and more particularly, to a method for forming an opening in an insulating layer formed on a conductive layer containing aluminum.
With the development of semiconductor technology to the LSI or VLSI scale, a semiconductor device usually has a multi-level conductive layer. If the conductive layer is formed at multiple levels, a via hole, serving as a contact passage, is formed in an insulating layer placed between upper and lower conductive layers to thereby connect upper and lower conductive layers.
FIGS. 1A-1E are sectional views for illustrating a general method for forming a via hole on a conductive layer made of a material containing aluminum.
Referring to FIG. 1A, a lower conductive layer 11 and a photoresist pattern 13 are formed. Specifically, FIG. 1A shows the steps of depositing a conductive material containing aluminum, i.e., aluminum or an aluminum alloy, on a lower structure 10 formed on a semiconductor substrate (not shown) to thereby form a lower conductive layer 11, coating an insulating material such as silicon oxide on lower conductive layer 11 to thereby form an insulating layer 12, coating a photoresist layer on insulating layer 12, and patterning the photoresist layer by an ordinary photolithography technique to thereby form a photoresist pattern 13 where a window through which the insulating layer placed on a via-hole-forming portion is exposed to the surface is formed.
FIG. 1B illustrates a step of forming the top portion 14 of the via hole. Here, a wet etching is performed on the insulating layer with photoresist pattern 13 acting as an etching mask, thereby isotropically etching insulating layer 12 by a predetermined thickness. This forms the top portion 14 of the via hole.
FIG. 1C illustrates a step of forming the bottom portion 15 of the via hole. In this step, the remaining insulating layer is etched until the top surface of the lower conductive layer 11 is exposed, by an anisotropical etching like reactive ion etching (RIE), thereby forming the bottom 15 of the via hole. Then, to insure that lower conductive layer 11 is fully exposed, some degree of over-etching is performed on the lower conductive layer.
FIG. 1D illustrates a step of removing the photoresist pattern. This step includes removing the photoresist pattern (reference number 13 of FIG. 1C) in an ordinary way, by ashing with O.sub.2 plasma and stripping with a chemical solution.
FIG. 1E illustrates a step of forming upper conductive layer 18, by depositing a conductive material on the resultant structure.
As the packing density of a semiconductor device increases, an area of the plane of the via hole decreases whereas its aspect ratio increases. For this reason, the step coverage of a conductive material to be deposited on the via hole becomes poor, and a void may be created.
In order to reduce the aspect ratio of a via hole, as discussed in the aforementioned general method for forming the via hole, the top portion of the via hole is formed via isotropic etching and the bottom portion thereof is anisotropically etched, so that the top of the via hole has a larger diameter than its bottom.
As another result of semiconductor devices being packed more densely, the topography of a lower conductive layer becomes more uneven. This is due to the lower structure. Thus, the insulating layer formed thereon has different thicknesses in different portions.
In forming a via hole for interconnecting the upper and lower conductive layers, if the insulating layer formed on the lower conductive layer in a specific portion is thinner than that formed on some other portion of the lower conductive layer, the etching process for forming the via hole must still conform to the thicker portions in order to reliably secure the connection of the upper and lower conductive layers. Therefore, the via hole formed on the thinner portion of the insulating layer is relatively over-etched as compared with one formed on the thicker portion. That is, the etching should continue even after the completion of the thinner-location via hole because the thicker-location via hole is not yet completely formed, so that the surface of the lower conductive layer formed on the portion where the thinner insulating layer is formed is etched by a certain depth (over-etched).
For the etching for forming the via hole, a fluorocarbon-containing gas such as CF.sub.4 or CHF.sub.3 is generally used. During etching, these gases react with a material of the insulating layer, thereby producing a polymer having a structural formula of CF.sub.X where X is 2, 3 or 4. Particularly, in over-etching, the gases react with aluminum activated in the exposed conductive layer, thereby producing a nonvolatile by-product such as AlF.sub.3. The amount of the nonvolatile by-product increases as the amount of over-etching increases.
The polymer produced in the etching of the insulating layer is easy to remove in a succeeding process. However, the nonvolatile by-product generated by the reaction of aluminum and gas is not completely removed even by the succeeding process of ashing and stripping, and remains stuck to the surface of the conductive layer inside the via hole. This remaining by-product prevents proper electric connection in a succeeding interconnection process, thus increasing the rate of defective products and reducing the reliability of a manufactured semiconductor device.
In FIGS. 1C-1E, reference number 16 represents the polymer by-product of the etching of the insulating layer, and reference number 17 indicates the nonvolatile by-product generated in the over-etching process.
The generation of nonvolatile by-product can be prevented by depositing another metal layer on the lower conductive layer, such that the lower conductive layer is not formed only of a metal material containing aluminum. Therefore, the metal material containing aluminum is not directly etched in the over-etching for forming the via hole. For instance, in U.S. Pat. No. 4,948,459 (filed on Jan. 4, 1989 and entitled "Method of Enabling Electrical Connection to a Substructure Forming Part of an Electronic Device" by Josephus M. F. G. van Laarhoven et al.), a second conductive layer made of a material not containing aluminum, for instance, titanium or tungsten, is formed on a first conductive layer containing aluminum so that the first conductive layer is not directly exposed to plasma when forming a via hole. This prevents by-product from being created. This added step, however, further complicates the process.